1. Field of the Invention
The present invention relates to synchronization circuitry that receives data to be employed in a mobile FM (Frequency Modulation) multiplex broadcasting system to establish synchronization.
2. Description of the Background Art
Conventionally, some synchronization circuitry is used which receives data, particularly frame data constructed with a plurality of blocks, which is employed in mobile FM multiplex broadcasting systems to establish block synchronization and frame synchronization.
In such frame data, the first 16 bits of each block represents a block identity code (BIC). Each block has one of plural kinds of BICs, for example, one of four BICs: BIC1, BIC2, BIC3, and BIC4.
It is known that the block identity code occupies the first 16 bits of one block. If a block identity code is detected by checking received data bits one by one, the bit numbers in one block of received data bits are found and therefore block synchronization can be determined according to the bit numbers. For example, in the case where the number of block synchronization backward protection stages is three, if block identity codes can be detected from the three consecutive blocks it may be determined that block synchronization has been established.
There are cases where block identity codes vary between their blocks. In the case where the arrangement of blocks in one frame is fixed, the position at which a block identity code changes to another different block code, i.e. the block number of a frame change point is also fixed. Every time a block identity code is detected from received data, a change pattern from the previously detected block identity code is obtained. Therefore, since the block number of a frame change point can be obtained based on the change pattern, frame synchronization can be determined according to the block numbers of frame change points.
Conventional synchronization circuitry is operative by 16-kbit/sec clock signals for FM multiplex broadcasting, and therefore the data transmission rate of received data is 16 kbit/sec. When receiving one frame of data which contains 272 blocks each consisting of 288 bits, such synchronization circuitry may have a shift register of 864 bits to store received data. This shift register is able to store blocks of data corresponding to the number of block synchronization backward protection stages, for instance, three blocks of received data.
Such synchronization circuitry is provided with as many BIC comparators as the block synchronization backward protection stages, for example, three BIC comparators. The BIC comparators receive one data bit at a time from three blocks of the shift register, and compare 16 consecutive data bits with reference block identity codes to determine whether or not the data bits coincide with any of the reference block identity codes. If the number of inconsistent bits between them is within an allowable number of errors, they may be considered to coincide with each other.
The synchronization circuitry is also provided with a block synchronizer that generates a block synchronous signal in response to the comparison results of the three BIC comparators. If the number of block synchronization backward protection stages is three, when the three comparison results coincide with block identity codes at the same time, the block synchronizer determines that block synchronization has been established. The synchronization circuitry has a block counter that counts a bit number in response to a clock signal. The block identity code is 16 bits, and therefore if a count value of “17” is set to the block counter when block synchronization is established, the block counter can obtain correct block count values corresponding to bit numbers thereafter.
If the BIC comparator detects a block identity code, it holds the block identity code in a BIC holder. The detected block identity code is also output to a frame change detector. The frame change detector detects a change between the detected block identity code obtained from the BIC comparator and the previous block identity code held in the BIC holder. If the change coincides with a change pattern representing a frame change, it is stored in a frame change register.
The synchronization circuitry further has a frame synchronizer that generates a frame synchronous signal in response to the change pattern obtained from the frame change register. If the number of frame protection stages is two, the frame synchronizer detects whether or not two consecutive change patterns stored in the register are arranged in the order of block number. If they are arranged in order, the frame synchronizer determines that frame synchronization has been established.
The synchronization circuitry has a frame counter that counts the number of blocks each time the block count value becomes “288”. If a count value, which represents a block number corresponding to a frame change point when frame synchronization is established, is set to the frame counter, it can obtain a correct frame count value even thereafter.
In the case of testing such synchronization circuitry, the operating state of the synchronization circuitry can be confirmed by receiving test data constructed with 272 blocks each having 288 bits, and monitoring a block synchronous signal, a block count value, a frame synchronous signal, and a frame count value.
For instance, an error adder disclosed in Japanese patent laid-open publication No. 141056/1994 is of a type incorporated into a digital radio receiver, and can test the error correcting function and the synchronous detection and protection function of the receiver by adding error bits to a received signal or rendering a frame synchronous pattern erroneous.
There are situations where the synchronization circuitry tests block synchronization, using an allowable error bit number for a block identity code as a parameter, or tests frame synchronization, using a frame changing point between block identity codes as a parameter. Tests must be performed not only when reception conditions are good, but also even when they are bad. However, it is fairly difficult for conventional synchronization circuitry to perform tests when reception conditions are bad.
In the case where the number of block synchronization protection stages is three, it is necessary to detect three block identity codes, so that at least two blocks and one block identity code, i.e. 592 data bits (=288×2+16) are necessary. Since the data transmission rate in conventional synchronization circuitry is 16 kbit/sec, the test of one block requires 37 msec. Because one frame consists of 272 blocks, the test of frame synchronization requires about 10 sec. Therefore, when various conditions are considered together, an extremely long test time becomes necessary.